Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!bloom-beacon!athena.mit.edu!tada
From: tada@athena.mit.edu (Michael Zehr)
Newsgroups: comp.arch
Subject: Re: RISC as a "technology window"?
Summary: multiple CPU chips
Message-ID: <10078@bloom-beacon.MIT.EDU>
Date: 24 Mar 89 18:56:36 GMT
References: <1552@vicom.COM> <15690@cup.portal.com> <1562@vicom.COM> <15702@clover.ICO.ISC.COM> <27681@apple.Apple.COM> <15695@winchester.mips.COM>
Sender: daemon@bloom-beacon.MIT.EDU
Reply-To: tada@athena.mit.edu (Michael Zehr)
Organization: Massachusetts Institute of Technology
Lines: 31

In article <15695@winchester.mips.COM> mash@mips.COM (John Mashey) writes:
>In article <27681@apple.Apple.COM> jrg@Apple.COM (John R. Galloway) writes:
>>In article <15702@clover.ICO.ISC.COM>, rcd@ico.ISC.COM (Dick Dunn) writes:
>>> In article <37196@bbn.COM>, slackey@bbn.com (Stan Lackey) writes:
>>> > RISC is indeed a technology window, driven largely by the amount of
>>> > stuff you can fit in a chip...
>>> OK, fair 'nuff.  As soon as we can put an unlimited amount of stuff on a
>>Well actually only while the "extra" space is less than a full cpu, as soon
>I suspect it will be some time before people replicate the CPUs on
>a chip, just because there's nothing else to do with the silicon.
>	a) It's hard to get enough bandwidth in and out of these chips,
>		i.e., I/Os cost money.

Professor Daly (sp?) of MIT has been saying something along those lines
for a couple years.  instead of having a whole bunch of memory chips
with one path to a fast CPU and have a cache to prevent slow accesses,
take each of those memory chips, halve the amoune of memory on them, and
put a CPU on it.  you no longer have a memory banchwith problem, because
the memory and CPU are on the same (small, easy-to-make) chip.  instead
of putting a cache on the chip (you don't need one), put a
communications circuit to transfer data to the other chips.

If you're interested in more information, he's working on something
called a J-machine, which will probably be in prototype stage sometime
this summer (i think?).

which would you rather have -- one CPU that runs at 50 MIPS with 72,
1Mbit memory chips (8 Megabytes * 9 chips per byte) or 72, 10 MIPS
processors and 4 Megabytes of memory split among them?

-michael j zehr