Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!rutgers!rochester!pt.cs.cmu.edu!MATHOM.GANDALF.CS.CMU.EDU!lindsay
From: lindsay@MATHOM.GANDALF.CS.CMU.EDU (Donald Lindsay)
Newsgroups: comp.arch
Subject: ECL 88000
Message-ID: <4559@pt.cs.cmu.edu>
Date: 24 Mar 89 19:43:00 GMT
Organization: Carnegie-Mellon University, CS/RI
Lines: 48


What follows is the publicly revealed information about Data General's
upcoming ECL M88000. I'm posting it in the hopes of stirring up a good
fight, particularly as concerns the cache organization. Perhaps the
nice people doing the ECL MIPS, the GaAs MIPSes, the ECL SPARC, and the
GaAs SPARC, would like equal time.


Technology:
   Motorola ECL gate arrays, 50,000 gates each.
   Stated as 40 watts per chip, but surely they meant per-chip-set.
   Air cooled.

CPU:
   One ECL chip for integer, one for float. Two copies of the registers.
   140 MHz ( ~7 ns clock ).
   Pipeline can overlap Integer/FADD/FMUL execution.
   DFADD takes 4 clocks, no pipelining within FADD unit.
   SFMUL takes 6 clocks, no pipelining within FMUL unit.
   DFMUL takes 8 clocks, no pipelining within FMUL unit.

Cache/MMU:
   One ECL chip plus static RAM chips.
   Four caches, not two.
   First  level I & D caches have 5  ns access chips ( 2Kx1 is mentioned )
   Second level I & D caches have 12 ns access chips ( 8Kx1 is mentioned )
   First  level can be 8KB-256KB, 16KB is mentioned.
   Second level can be 64KB-1MB, 128KB is mentioned.
   Not clear if those sizes are for I & D together or separately.

Cache timing:
   If first level hits, it can supply 1 op word + 1 data word per clock.
   Store bandwidth is one data word per two clocks.
   Third op after a load op, can use the loaded data without causing a stall.
   A first-level read miss, that hits in the second level,
      costs two or three extra clocks, I'm not sure which.

Cache organization:
   All caches are direct mapped.
   First level uses virtual addresses, second level uses physical.
   First level always writes through to the second.
   Second level's write policy is software selectable.
   Second level can translate physical addresses to virtual,
      presumably on behalf of the bus snooper.
      It insures that the first level never has multiple
      entries for one physical address.
-- 
Don		D.C.Lindsay 	Carnegie Mellon School of Computer Science
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