Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!ames!lll-lcc!lll-winken!uunet!pdn!rnms1!alan
From: alan@rnms1.paradyne.com (0000-Alan Lovejoy(0000))
Newsgroups: comp.arch
Subject: Re: RISC as a "technology window"?
Message-ID: <5855@pdn.paradyne.com>
Date: 27 Mar 89 03:24:13 GMT
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Reply-To: alan@rnms1.paradyne.com (0000-Alan Lovejoy)
Organization: AT&T Paradyne, Largo, Florida
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In article <16231@cup.portal.com> bcase@cup.portal.com (Brian bcase Case) writes:
>>The general consensus seems to be that
>>the primary determinant is the physical implementation, but that the logical
>>architecture heavily influences to what extent RISCy implementation techniques
>>can be used.

>Right, except that I don't agree that the primiary determinant is the
>physical implementation.  A RISC is an architecture that *permits* a *clean*,
>high-performance implementation.  A CISC architecture might be able to use
>some high-performance implementation tricks, but cleanliness is next to
>RISCyness.  The cleanliness becomes very important when superscalar
>implementations, and probably multiple-processor-per-chip implementations,
>are designed.

Hmmm...  Isn't there an important connection between the chip implementation
technology (e.g., silicon transisitors, quantum circuits, photonics, vacuum
tubes...) and the problem of designing an efficient implementation of a
logical architecture?  Logical architectures that cannot be efficiently
implemented in NMOS might have no such problems in an optical computer.
If it is the logical architecture that is the primary determinant, then
whether something is a RISC depends on the current implementation technology.

Or am I missing something?


Alan Lovejoy; alan@pdn; 813-530-2211; AT&T Paradyne: 8550 Ulmerton, Largo, FL.
Disclaimer: I do not speak for AT&T Paradyne.  They do not speak for me. 
__American Investment Deficiency Syndrome => No resistance to foreign invasion.
Motto: If nanomachines will be able to reconstruct you, YOU AREN'T DEAD YET.