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From: stevew@wyse.wyse.com (Steve Wilson xttemp dept303)
Newsgroups: comp.arch
Subject: Re: RISC as a "technology window"?
Message-ID: <2173@wyse.wyse.com>
Date: 27 Mar 89 20:17:00 GMT
References: <1552@vicom.COM> <15690@cup.portal.com> <1562@vicom.COM> <15702@clover.ICO.ISC.COM> <27681@apple.Apple.COM> <15695@winchester.mips.COM> <10078@bloom-beacon.MIT.EDU>
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Reply-To: stevew@wyse.UUCP (Steve Wilson xttemp dept303)
Organization: Wyse Technology
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In article <10078@bloom-beacon.MIT.EDU> tada@athena.mit.edu (Michael Zehr) writes:
>
>which would you rather have -- one CPU that runs at 50 MIPS with 72,
>1Mbit memory chips (8 Megabytes * 9 chips per byte) or 72, 10 MIPS
>processors and 4 Megabytes of memory split among them?
>
>-michael j zehr

One CPU that runs at 50 mips with 72 1Mbit memory chips. I already
know how to program a single CPU ;-)



Steve Wilson

The above is my opinion, not those of my employer.