Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!csd4.milw.wisc.edu!lll-winken!uunet!tektronix!orca!tekecs!frip!andrew
From: andrew@frip.wv.tek.com (Andrew Klossner)
Newsgroups: comp.arch
Subject: mapping bothers physical i-cache? (was Re: i860 cache flushing)
Message-ID: <11204@tekecs.GWD.TEK.COM>
Date: 28 Mar 89 21:08:39 GMT
References: <15888@winchester.mips.COM> <39485@oliveb.olivetti.com> <24958@amdcad.AMD.COM> <39722@oliveb.olivetti.com> <665@garcon.cso.uiuc.edu>
Sender: andrew@tekecs.GWD.TEK.COM
Organization: Tektronix, Wilsonville, Oregon
Lines: 15

[]

	"About physical i-caches: it is not clear to me that a context
	switch may not render lines in even physical i-caches invalid.
	In a processor where the i-fetch unit is what fills the
	i-cache, there is a chance that after a context switch the OS
	will map a different page (of instructions, perhaps) into a
	physical page frame that has some lines in the i-cache."

Huh?  If both the i-cache and the d-cache are physical, then it doesn't
matter what page mappings the OS sets up, since that's all upstream of
the cache.

  -=- Andrew Klossner   (uunet!tektronix!orca!frip!andrew)      [UUCP]
                        (andrew%frip.wv.tek.com@relay.cs.net)   [ARPA]