Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!ames!lll-lcc!lll-winken!uunet!portal!cup.portal.com!bcase
From: bcase@cup.portal.com (Brian bcase Case)
Newsgroups: comp.arch
Subject: Re: How to use silicon (was Re: Intel/MIPS Dhrystone ratio)
Message-ID: <16352@cup.portal.com>
Date: 28 Mar 89 17:52:09 GMT
References: <37196@bbn.COM> <1989Mar16.190043.23227@utzoo.uucp> <24889@amdcad.AMD.COM> <355@bnr-fos.UUCP> <27600@apple.Apple.COM> <16080@cup.portal.com> <27711@apple.Apple.COM> <16156@cup.portal.com> <5854@pdn.paradyne.com>
Organization: The Portal System (TM)
Lines: 16

>If all instructions were...say...forty eight bits long, then this machine
>should achieve 25% more work per instruction bit than conventional RISCs.

Two comments:  non-power-of-two-sized instructions are not a good idea
(you can't fit an integral number into a page, unless your pages are
non-power-of-two-sized, and that is a *bad* idea).  Also, you should
look at Wulf's WM machine; his architecture is designed along the same
lines, i.e., two things per instruction, but WM has 32-bit instructions
and two ALU ops per instruction and data streaming (i.e., loads and
stores happen without an explicit initiating load or store instruction).
Bill, if you're out there, what's the status of the WM machine?

Your idea is a good one:  it is VLIW, in some sense.  However, it is
probably not possible to keep the load/store side of the instruction
busy a large fraction of the time in general code, although scientific
codes can probably take advantage of this "vector" caapability.