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From: jesup@cbmvax.UUCP (Randell Jesup)
Newsgroups: comp.arch
Subject: Re: RISC as a "technology window"?
Message-ID: <6418@cbmvax.UUCP>
Date: 29 Mar 89 01:25:10 GMT
References: <1552@vicom.COM> <15690@cup.portal.com> <1562@vicom.COM> <15702@clover.ICO.ISC.COM> <27681@apple.Apple.COM> <15695@winchester.mips.COM> <10078@bloom-beacon.MIT.EDU>
Reply-To: jesup@cbmvax.UUCP (Randell Jesup)
Organization: Commodore Technology, West Chester, PA
Lines: 15

In article <10078@bloom-beacon.MIT.EDU> tada@athena.mit.edu (Michael Zehr) writes:
>Professor Daly (sp?) of MIT has been saying something along those lines
>for a couple years.  instead of having a whole bunch of memory chips
>with one path to a fast CPU and have a cache to prevent slow accesses,
>take each of those memory chips, halve the amoune of memory on them, and
>put a CPU on it.  you no longer have a memory banchwith problem, because
>the memory and CPU are on the same (small, easy-to-make) chip.  instead
>of putting a cache on the chip (you don't need one), put a
>communications circuit to transfer data to the other chips.

	Sounds a lot like a transputer... how is it different? (other than
being implemented in a more modern process)

-- 
Randell Jesup, Commodore Engineering {uunet|rutgers|allegra}!cbmvax!jesup