Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!unmvax!ncar!ames!oliveb!pyramid!prls!mips!keith
From: keith@mips.COM (Keith Garrett)
Newsgroups: comp.arch
Subject: Re: RISC as a "technology window"?
Message-ID: <16181@gumby.mips.COM>
Date: 29 Mar 89 22:58:11 GMT
References: <1552@vicom.COM> <15690@cup.portal.com> <1562@vicom.COM> <15702@clover.ICO.ISC.COM> <27681@apple.Apple.COM> <15695@winchester.mips.COM> <22974@ames.arc.nasa.gov> <6416@cbmvax.UUCP>
Reply-To: keith@mips.COM (Keith Garrett)
Organization: MIPS Computer Systems, Sunnyvale, CA
Lines: 14

In article <6416@cbmvax.UUCP> jesup@cbmvax.UUCP (Randell Jesup) writes:
>
>	The problem with this is that off-chip access is slower than on-chip,
>due to signal load and pad static-protection capacitance.

there are also serious speed-of-light considerations. chip to chip path lengths
are considerably longer than on-chip paths. this effect will become worse in
the future as transistor speeds become faster, and transistor spacings become
less. connect technologies that don't support terminated transmission lines
(can you say TTL??) have worse problems due to long bus settling times.
-- 
Keith Garrett        "This is *MY* opinion, OBVIOUSLY"
UUCP: keith@mips.com  or  {ames,decwrl,prls}!mips!keith
USPS: Mips Computer Systems,930 Arques Ave,Sunnyvale,Ca. 94086