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From: keith@mips.COM (Keith Garrett)
Newsgroups: comp.arch
Subject: Re: i860 cache flushing
Message-ID: <16185@gumby.mips.COM>
Date: 29 Mar 89 23:10:32 GMT
References: <15888@winchester.mips.COM> <39485@oliveb.olivetti.com> <24958@amdcad.AMD.COM> <39722@oliveb.olivetti.com> <665@garcon.cso.uiuc.edu>
Reply-To: keith@mips.COM (Keith Garrett)
Organization: MIPS Computer Systems, Sunnyvale, CA
Lines: 15

In article <665@garcon.cso.uiuc.edu> conte@bach.csg.uiuc.edu.UUCP (Tom Conte) writes:
>About physical i-caches: it is not clear to me that a context switch
>may not render lines in even physical i-caches invalid.  In a processor
>where the i-fetch unit is what fills the i-cache, there is a chance
>that after a context switch the OS will map a different page (of
>instructions, perhaps) into a physical page frame that has some lines
>in the i-cache.

this is a page swap, not a context switch. you have to flush/invalidate
both physical and virtual caches (tlb's also) for this, but the frequency
should be alot lower.
-- 
Keith Garrett        "This is *MY* opinion, OBVIOUSLY"
UUCP: keith@mips.com  or  {ames,decwrl,prls}!mips!keith
USPS: Mips Computer Systems,930 Arques Ave,Sunnyvale,Ca. 94086