Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!bbn!oberon!ucla-cs!frazier
From: frazier@oahu.cs.ucla.edu (Greg Frazier)
Newsgroups: comp.arch
Subject: Re: RISC as a "technology window"?
Message-ID: <22373@shemp.CS.UCLA.EDU>
Date: 29 Mar 89 23:08:52 GMT
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Reply-To: frazier@cs.ucla.edu (Greg Frazier)
Organization: UCLA Computer Science Department
Lines: 39

In article <6418@cbmvax.UUCP> jesup@cbmvax.UUCP (Randell Jesup) writes:
>In article <10078@bloom-beacon.MIT.EDU> tada@athena.mit.edu (Michael Zehr) writes:
>>Professor Daly (sp?) of MIT has been saying something along those lines
>>for a couple years.  instead of having a whole bunch of memory chips
>>with one path to a fast CPU and have a cache to prevent slow accesses,
>>take each of those memory chips, halve the amoune of memory on them, and
>>put a CPU on it.  you no longer have a memory banchwith problem, because
>	Sounds a lot like a transputer... how is it different? (other than
>being implemented in a more modern process)
>

There are several dramatic differences.  The Message Driven Processor
(MDP) directly implements `actors' (I think that's the term).  The
chip actually contains two processors - one to handle incoming
and outgoing msgs, the other to execute code.  Arriving msgs directly
point to code in memory to be executed.  The machine as a whole
supports a global address space, which makes this possible.  Also,
the memory can be used as context-addressable, so that arriving
msgs can refer to code symbolically.  The idea is that this directly
supports object-oriented programming, where each object resides on
a node.  Each node is expected to send and receive msgs on the order
of every 20 inst'ns.  Msg routing and forwarding are handled by
a Torus Routing Chip-style-router which also resides on the chip.
The most obvious problem with this approach is that only 16k memory
can accompany a 4 MIP processor (the general rule of thumb is
1M of memory/1 MIP of processor).  Dally, et. al. claim that this
rule of thumb does not apply because of the global nature of the
memory, that with 64k nodes they have and address space of 2^30
bytes.  Of course, they also have 256k MIPS of processor, but
they didn't memtion that...

So, all in all, this is a VERY different beast from the Transputer.

Greg Frazier
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