Newsgroups: comp.sys.cbm
Path: utzoo!utgpu!jarvis.csri.toronto.edu!godzilla.eecg.toronto.edu!leblanc
From: leblanc@eecg.toronto.edu (Marcel LeBlanc)
Subject: Re: C128,C128D, and C128C??? Questions
Message-ID: <89Mar20.194245est.2737@godzilla.eecg.toronto.edu>
Organization: EECG, University of Toronto
References: <1856.2423BC06@isishq.FIDONET.ORG>
Date: Mon, 20 Mar 89 19:42:43 EST

In article <1856.2423BC06@isishq.FIDONET.ORG> izot@f171.n221.z1.FIDONET.ORG (Geoffrey Welsh) writes:
>
> > From: fred@cbmvax.UUCP (Fred Bowen)
> > Message-ID: <6222@cbmvax.UUCP>
> 
> >>I have plenty of "why didn't you do that
> >>in the first place" questions for the designers of the C128...
> >
> >I have plenty of "why didn't we do that" answers, BTW...
 ...
>(3) I find it incredibly amusing that the Z80 runs at an effective 2 MHz even 
>though the VIC-II is enabled because it runs 4 MHz, 2 cycles on and 2 off. 
>Would producing a 4 MHz 8502 have ben so expensive that a similar scheme could 
>not have been used to allow 128 mode to support 2 MHz, even in 40-column mode? 
>Better yet, why does there not seem to be a way to shut doen the VIC-II chip 
>in CP/M mode and run the Z80 flat out at 4 MHz (Jeez, it would have been nice 
>to do that in C128 mode as well)...

I'm not sure of exactly what it is you're trying to say, but it looks like
you're equating MHz on 8502 with MHz on Z80, which is completely false.  A
2Mhz 6502 is (almost) 4 times faster than a 2Mhz Z80.  This is because
memory (or IO) accesses on a Z80 take 3-4 cycles, whereas the same operation
on a 6502 takes only one cycle (yes, the 6502 was an early RISC :-) ).  So
even if you could get the Z80 to run flat out at 4MHz, it would still be
only a little more than half the speed of the 8502 at 2MHz.  But then, I
guess CP/M can use all the speed it can get...

Marcel A. LeBlanc	  | University of Toronto -- Toronto, Canada
leblanc@eecg.toronto.edu  | also: LMS Technologies Ltd, Fredericton, NB, Canada
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