Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!ucbvax!ernie.Berkeley.EDU!jas From: jas@ernie.Berkeley.EDU (Jim Shankland) Newsgroups: comp.arch Subject: Re: RT/PC Unaligned Accesses Message-ID: <28664@ucbvax.BERKELEY.EDU> Date: 3 Apr 89 20:39:22 GMT References: <4618@pt.cs.cmu.edu> <4628@pt.cs.cmu.edu> Sender: usenet@ucbvax.BERKELEY.EDU Reply-To: jas@ernie.Berkeley.EDU (Jim Shankland) Organization: University of California, Berkeley Lines: 18 The cases for faulting on unaligned instructions and data accesses (e.g., MIPS, 68010, et al.) rather than dealing with them correctly in hardware (e.g., VAX) is stronger than the case for silently forcing the 1 or 2 LSB's to 0, as the RT/PC does. Sure, correct programs will run correctly; but correct programs of any respectable size are almost unheard of. Consider the following reductio ad absurdum: My new processor does not fault on data references beyond the bounds of a process's address space; instead, it silently reads random data. This saved me a hunk of silicon. Correct programs still run correctly; only programs that dereference wild pointers get into trouble, and those are broken anyway. Jim Shankland jas@ernie.berkeley.edu "Blame it on the lies that killed us, blame it on the truth that ran us down"