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From: tim@crackle.amd.com (Tim Olson)
Newsgroups: comp.arch,comp.lang.c
Subject: Re: looking for >32-bit address space [and how will C handle it]
Message-ID: <25106@amdcad.AMD.COM>
Date: 5 Apr 89 02:40:48 GMT
References: <16568@winchester.mips.COM> <1032@myrias.UUCP> <12289@reed.UUCP> <11968@pasteur.Berkeley.EDU>
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Reply-To: tim@amd.com (Tim Olson)
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In article <11968@pasteur.Berkeley.EDU> faustus@dogwood.Berkeley.EDU (Wayne A. Christopher) writes:
| In article <16568@winchester.mips.COM>, mash@mips.COM (John Mashey) writes:
| > In article <12289@reed.UUCP> mdr@reed.UUCP (Mike Rutenberg) writes:
| > >>Are there any micros or chipsets out there that support an address space
| > >>larger than 32 bits?
| >
| > 	2) Flat 64-bit addressing has been, and will be for a lonnng time,
| > 	too costly for most micros.
| 
| Take a look at this month's Spectrum -- there's an article about the
| Intel i680 chip, which seems to have a flat 64-bit address space.
| We'll have to see how quickly this chip catches on -- it looks really
| hot (it benchmarks at twice the Dhrystones of the MIPS chip), but for
| manufacturers who don't want to double the size of their external bus
| it may be a bit too much.

Quoting from the i860 "64-bit microprocessor" manual, Chapter 4
(Addressing):

	"Memory is addressed in byte units with a paged virtual-address
	space of 2^32 bytes. ... Address arithmetic is performed using
	32-bit input values and produces 32-bit results."

The i860 really is a 32-bit machine -- the 64-bit label seems to come
from the 64-bit external bus, which is used to fetch two
instructions/data words at a time for cache reload.

Well, there is some support for 64-bit integers in the graphics unit
(addition and subtraction), but not in general.


	-- Tim Olson
	Advanced Micro Devices
	(tim@amd.com)