Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!ucbvax!hplabs!hpda!hpcuhb!gupta
From: gupta@hpcuhb.HP.COM (Mayank Gupta)
Newsgroups: comp.arch
Subject: Re: looking for >32-bit address space
Message-ID: <3830005@hpcuhb.HP.COM>
Date: 4 Apr 89 21:28:34 GMT
References: <1032@myrias.UUCP>
Organization: Hewlett Packard, Cupertino
Lines: 32


> 1) can you say more about what this "Level x compliance" means?
>    (Does that mean that you can build HP PA machines with 32/32, and that's
>    called Level 0?  or does it mean something other than compliance with
>    an HP-internal spec?)

   This is just a flexibility provided to the implementer of the CPU to choose
  from.  Yes somebody could make a 32 bit Virtual and 32 bit physical address
  (Level 0) CPU and still be called a HP-PA.  To this date, (to my knowledge)
  no HP-PA Level 0 has been made.  This option leaves the door open for someone
  to make a CPU for a embedded controller type application or something like
  intel's N-10.

  Virtual space is segmented as 2^0  spaces of 2^32 bytes for Level 0.
                                2^16 spaces of 2^32 bytes for Level 1.
                                2^32 spaces of 2^32 bytes for Level 2.

> 2) I suspect that the original question was looking for machines more like
>    some supercomputers, i.e., with 64-bit integers and addresses that are
>    used directly as such (which I don't think HP PA does: correct me if I'm
>    wrong, but aren't there segment registers that can be controlled by the
>    compilers, rather than 64-bit flat addresses?)

  Sorry, If I mis-interpreted the question.

  HP-PA is a 32 bit integer and 64 bit floating point architecture.
  There are 0, 16 or 32 bit (depending on Level) space registers in hardware
  TLBs.  Software PDIR is maintained with 64 bit virtual address in mind.
  
Mike Gupta
gupta@hpesomg
408-447-0390