Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!bloom-beacon!gatech!prism!loligo!bauer
From: bauer@loligo.cc.fsu.edu (Jeff Bauer)
Newsgroups: comp.arch
Subject: Re: MicroVAX emulation (really : DEC about-face)
Keywords: RISC, CISC
Message-ID: <573@loligo.cc.fsu.edu>
Date: 10 Apr 89 15:40:55 GMT
References: <807@microsoft.UUCP> <92634@sun.uucp> <13322@steinmetz.ge.com> <37515@bbn.COM> <514@dragos.UUCP>
Reply-To: bauer@loligo.cc.fsu.edu (Jeff Bauer)
Organization: Control Data Corporation
Lines: 54

In article <514@dragos.UUCP> ruiu@dragos.UUCP (dragos) writes:
>In article <37515@bbn.COM>, slackey@bbn.com (Stan Lackey) writes:
>>     I don't understand why it is OK for the RISC suppliers to supply
>>     reduced instruction sets, but if DEC does it it's evil.
>
>
>     Because Ken Olsen has repeatedly stated he dislikes RISC, and 
>     has on occasion declared that DEC will never sell a processor
>     they will call a RISC.   :-) :-) :-)
>
>-- 
>Dragos Ruiu  ruiu@dragos.UUCP  "Yes, Dragos is my first name."
>   ...alberta!edm!dragos!ruiu  "Why? Someone said it sounded like a nodename!"

Boy, all things do come around again...and again.

I have a copy of a paper from grad school days by Clark and Strecker of DEC
from Sept. '80; one of the early examples of RISC-bashing (and VAX crowing) 
right before the Berkeley RISC I.  In this case the authors blast points 
made earlier by Patterson & Ditzel in _The Case for the Reduced Instruction 
Set Computer_ (CAN, Oct. 1980) by making such nifty claims as [contents
quoted without permission and probably horribly out of context :) ] -

	o Ease of compiler-writing..."code generation in VAX compilers
	  is simplified by having them all [different address mode
	  instructions] (this is attested to by VAX compiler-writers)"

	o Regarding the probability of increased design errors ..
	  "How would Patterson and Ditzel compare the complexity of
	  the VAX-11/780 microcode to that of, say, an optimizing compiler?"

	o Considering CISC instructions executing in separate functional
	  units..."to speed up the multiply function on the RISC would
	  require a speed-up of the whole processor while speeding up the
	  multiply instruction on the CISC could be accomplished by
	  adding specialized data paths and control."

	o Challenging the "risc-takers"..."Casual evaluation of cost and
	  performance will not be sufficient unless the differences between
	  a RISC and a CISC are extreme, which is unlikely.  Paper designs
	  will not be enough."

	o And a block/parry..."Patterson and Ditzel suggest that marketing
	  strategy can increase the size or complexity of an instruction set.
	  We can state from first-hand knowledge that this is not true for
	  the VAX architecture."

Seems to me that some of the points only helped the early RISC-takers by
driving development to counter the CISC arguments.  Of course DEC is still
riding the VAX instruction set in many hardware guises, but they sure have
widened up their tunnel vision since 1980.
-- 
Jeff Bauer					bauer@loligo.cc.fsu.edu
Control Data Corporation			(904) 644-2591 ext. 113