Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!unmvax!polyslo!vega.acs.calpoly.edu!mdeale From: mdeale@vega.acs.calpoly.edu (Myron Deale) Newsgroups: comp.arch Subject: Re: 68040 and 80486 Message-ID: <10314@polyslo.CalPoly.EDU> Date: 14 Apr 89 17:34:31 GMT References: <1032@myrias.UUCP> <12289@reed.UUCP> <1049@myrias.UUCP> <1928@trantor.harris-atd.com> <17178@winchester.mips.COM> Sender: news@polyslo.CalPoly.EDU Reply-To: mdeale@vega.acs.calpoly.edu.UUCP (Myron Deale) Organization: Cal Poly State University -- San Luis Obispo Lines: 64 In article <17178@winchester.mips.COM> mash@mips.COM (John Mashey) writes: >In article <1928@trantor.harris-atd.com> thaker@trantor.harris-atd.com (Gautam Thaker) writes: >> 68040 and 486 have both >>been announced and there is almost nothing about them in >>the newsgroup. We have debated the question of which is >>better, the 386 or the 68030? > >Please, let us not fill THIS newsgroup with: > "I think the xxx will be better than yyy because xxx's vendor says > it will be N mips, and xxx's only says it will be M mips". > "The xxx's architecture is awful, hence yyy must be better." > "xxx has always lied, so yyy must be better". > "I heard a fourth-hand rumor that yyy will be really fas > "yyy runs at Z MHz more than xxx, so it must be better" > "xxx and yyy are both scum, zzz is clearly better anyway." > "xxx has more transistors than yyy, so it must be better" well spoken. > >Many of us would welcome DATA, especially as both these chips are important; >they're also interesting from an architectural view. [stuff deleted] >However, other than making gross estimates, it's pretty hard to say >very much about performance until one has: > c) Well-documented simulations of buildable systems. > (zero-wait-state main memories don't count :-) ahh, come on. What the heck :-) > OR, REALLY: > d) Lots of benchmarks run on real machines. > >How long will it be until one can get d)? (a while) yes, but I need to be thinking about design issues now. Rough estimates will do. Of course, I don't expect CISC to compete with RISC, at least not performance-wise. >-john mashey DISCLAIMER: >UUCP: {ames,decwrl,prls,pyramid}!mips!mash OR mash@mips.com if I had the dinero to subscribe to Microprocessor Report (hopefully Real Soon Now) you wouldn't see me requesting information/discussion on these chips. There was lots of traffic here when the i860 was announced, although I probably shouldn't rank the new CISC in its class. The "quiet" is somewhat unnerving. EDN and the other trade rags/journals/what-not will undoubtledly greet the new CISC with pomp and circumstance. I expect to read that in the coming month. But, I need to know a chip's strengths AND weaknesses. The strengths you tout; the weaknesses you *design* around and lend uniqueness. Not to denigrate them, but as you well know, EDN doesn't provide a complete picture. The net helps out in this respect. my other option is to "order blind." i.e. call the respective marketing dept's and impose on them as much as possible for information. For various reasons I'd like to cut down on this practice. so, could we have some discussion on the new CISC from interested / knowledgeable parties. [which (hopefully) includes mash]. Myron // mdeale@cosmos.ACS.CalPoly.EDU // "... but cleanliness is next to RISCyness." ++ bcase