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From: mac@uvacs.cs.Virginia.EDU (Alex Colvin)
Newsgroups: comp.arch
Subject: Re: RT/PC Unaligned Accesses
Summary: addressing mode ALU
Message-ID: <3086@uvacs.cs.Virginia.EDU>
Date: 14 Apr 89 13:10:49 GMT
References: <28200296@mcdurb>
Organization: University of Virginia
Lines: 10

> >that you can use the low order bits as free tag bits -- without runtime

> provide a mask that is implicitly ANDed with any {instruction,data} address
> before use -- this way you could place tag bits in the low bits, in the
> high bits, or in any bit you wanted (and not have to rely on features like

Most instruction addressing modes provide an adder, some also will do
limited shifting.  As long as we want AND and OR, let's just put in the
whole ALU.  This is sort of what the WM design does with its two opcodes.
Think of one as the addressing mode.  You want auto-increment by 17?