Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!bloom-beacon!bu-cs!buengc!bph
From: bph@buengc.BU.EDU (Blair P. Houghton)
Newsgroups: comp.lsi
Subject: Re: Wired-OR in VLSI
Message-ID: <2462@buengc.BU.EDU>
Date: 2 Apr 89 22:53:13 GMT
References: <41352@tut.cis.ohio-state.edu>
Reply-To: bph@buengc.bu.edu (Blair P. Houghton)
Followup-To: comp.lsi
Organization: Boston Univ. Col. of Eng.
Lines: 17

In article <41352@tut.cis.ohio-state.edu> Dik Lee <dlee@cis.ohio-state.edu> writes:
>I like to hear from people who have experience with wired-logic or
>know some references. I am interested in both nMOS and cMOS.

Putting pullups in parallel would render nMOS useless, unless there
were seperate cell-designs for each level of parallelism (i.e., design
with N cells in parallel, use versions of the N cells that have pullups
N-times the length of a standalone cell's pullup; now, explain to the
boss that the N-squared increase in pullup area and factor of max{N} cost
increase in cell-library maintenance is somehow involved in "savings"...)

Further, Wired-Or is anathema to CMOS.  The first time the pullup of
cell-A and the pulldown of cell-B simultaneously went "on", you'd be
working in a (most probably unbalanced) ratioed region, wherupon Vout
becomes (if you're lucky) about 2.5 volts.

				--Blair