Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!csd4.milw.wisc.edu!lll-winken!uunet!tektronix!tekig5!brianr
From: brianr@tekig5.PEN.TEK.COM (Brian Rhodefer)
Newsgroups: comp.lsi
Subject: Re: Wired-OR in VLSI
Message-ID: <3971@tekig5.PEN.TEK.COM>
Date: 4 Apr 89 03:52:50 GMT
References: <41352@tut.cis.ohio-state.edu> <2462@buengc.BU.EDU>
Reply-To: brianr@tekig5.PEN.TEK.COM (Brian Rhodefer)
Organization: Tektronix, Inc., Beaverton,  OR.
Lines: 14

I don't see why Wired-OR/AND logic would take any power whatever:
it's passive.  The `wired' node winds up with a lot of capacitance
on it, though, so it won't switch as fast as an active gate.
Occasionally, speed is of no concern, and a wired gate can be a win.

A colleague used wire-ANDed gates to construct a multiplexer that
effectively decoded his microprocessor peripheral's `read registers'.
The host micro's memory read cycles were slow enough, relative to
the speeds of the ASIC gates, that the wired-AND delivered adequate
performance, at a lower chip real-estate cost than active circuitry
would have required.


Brian RHodefer  !tektronix!tekig5!brianr