Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!ames!lll-winken!uunet!wucs1!jps
From: jps@wucs1.wustl.edu (James Sterbenz)
Newsgroups: comp.lsi
Subject: Re: Wired-OR in VLSI
Message-ID: <779@wucs1.wustl.edu>
Date: 4 Apr 89 19:28:20 GMT
References: <41352@tut.cis.ohio-state.edu> <2462@buengc.BU.EDU> <3971@tekig5.PEN.TEK.COM>
Reply-To: jps@wucs1.UUCP (James Sterbenz)
Organization: Washington University, St. Louis, MO
Lines: 22

In article <3971@tekig5.PEN.TEK.COM> brianr@tekig5.PEN.TEK.COM (Brian Rhodefer) writes:

>A colleague used wire-ANDed gates to construct a multiplexer that
>effectively decoded his microprocessor peripheral's `read registers'.
>The host micro's memory read cycles were slow enough, relative to
>the speeds of the ASIC gates, that the wired-AND delivered adequate
>performance, at a lower chip real-estate cost than active circuitry
>would have required.

Assuming that this is a standard passive mux, this isn't really wire-ANDing;
only the selected path is closed (two wires in CMOS, p and n halves
of the xmit gate).  This is more like dealing with tri-state, since
logic levels are not being anded, one is being passed through with
the others hi-Z.

Now bipolar LSI is a different matter, but I doubt that the original 
poster was considering this.
-- 
James Sterbenz  Computer and Communications Research Center
                Washington University in St. Louis 314-726-4203
INTERNET:       jps@wucs1.wustl.edu
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