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From: mark@mips.COM (Mark G. Johnson)
Newsgroups: comp.lsi.cad,comp.lsi
Subject: Faster than SPICE
Message-ID: <16857@obiwan.mips.COM>
Date: 8 Apr 89 17:18:37 GMT
Reply-To: mark@mips.COM (Mark G. Johnson)
Lines: 38


   
Sort of now and again one reads about improved algorithms for circuit
simulation, usually accompanied by results like " N times faster than
SPICE but just as accurate"  ( usually the reported N is >3 ).

	( In this note, I take "circuit simulation" to mean transient
	analysis of _general_ networks of transistors, sources, and
	passive elements ... maybe looking at the step response of an
	opamp, maybe looking at the delay of a 32-bit adder in ECL,
	maybe investigating the MSB-glitch when the inputs to a DAC
        transition from 0111111 to 1000000, and maybe looking at the
	behavior of a flipflop with near-coincident inputs (producing
	metastability).  In short, a _general_ simulator, not something
	that handles *only* monotonic-waveform logic gates.)

Are any of youse (what a crummy word for 2nd person plural) out there
actively _using_ such a simulator?  If so could you please post a
summary of your experience with such beasties?  I'm especially interested
in the average, and the worst-case-ever-seen, runtime ratio between the
fast simulator and SPICE.  What's the difference between average-
and worst-case behavior?  Is the fast simulator faster for only
some kinds of circuits, etc?


  (We're doing inductive-ground-bounce studies, with octal CMOS (FCTA)
   chips driving an array of dram SIMM modules.  We find that for one of
   the flavors of SPICE, Berkeley 2G.6, the simulations run slowly.
   Perhaps [only a guess] it's because every single node in the entire
   simulation (both on- and off-chip) is inductively ringing at hundreds
   of MHz so the "activity" is high and the timesteps are very short
   [a guess].)

Thanks very much,
-- 
 -- Mark Johnson	
 	MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086
	...!decwrl!mips!mark	(408) 991-0208