Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!ncar!tank!eecae!cps3xx!usenet
From: usenet@cps3xx.UUCP (Usenet file owner)
Newsgroups: comp.os.cpm
Subject: Re: New processor rumour
Message-ID: <2381@cps3xx.UUCP>
Date: 5 Apr 89 22:26:21 GMT
References: <240@ericom.ericsson.se> <2259@sigma.UUCP>
Reply-To: beyer@frith.UUCP (Don W Beyer)
Organization: Engineering, Michigan State University, E. Lansing
Lines: 13

In article <2259@sigma.UUCP> bill@sigma.UUCP (William Swan) writes:
>Z280:	("Preliminary Product Specification")
>	20 MHz CMOS pipelined Z80 superset with MMU addressing up to 16
>	Mbytes, 3 16-bit counter-timers, 4 DMA channels, full-duplex UART,
>	on-chip 256-byte instruction and data associative cache, co- and
>	multi-processor support, etc. No mention of multiply/divide...

My copy of the preliminary BOOK for the Z280 shows all sorts of
Multiply and divide instructions.  Zilog decided to define a plethora of
new data types for this processor, so for each type there exists a mult/
divide instruction.  

I agree, I won't believe it untill _I_ see it either!