Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!rutgers!uwvax!astroatc!nicmad!madnix!perry
From: perry@madnix.UUCP (Perry Kivolowitz)
Newsgroups: comp.sys.amiga
Subject: Re: AmigaDos 1.3 (dh0: vs ASDG 8mb board)
Message-ID: <593@madnix.UUCP>
Date: 6 Apr 89 16:04:39 GMT
References: <95522@sun.Eng.Sun.COM> <584@madnix.UUCP> <16593@cup.portal.com>
Reply-To: perry@madnix.UUCP (Perry Kivolowitz)
Distribution: usa
Organization: ASDG Incorporated
Lines: 65

In article <16593@cup.portal.com> Sullivan@cup.portal.com (sullivan - segall) writes:
>There is in my mind, some question as to whether or not the ASDG boards
>should rely on any timing peculiarities of the Amigas.  Everyone wants 
>to cut corners to keep the chip count, and therefor the cost of their

First, ASDG does not cut corners. You refer to chip count...keeping costs
down? Pardon me,  but  noone has ever accused ASDG of having a sparse in-
expensive board before. :-)

>be robust on input and legal on output.  Accepting obvious timing flaws
>(such as not asserting some signal before cycle X) is a design requirement
>in a system where multiple vendors will be playing with those signals.

Let's see...``Accepting obvious timing flaws is a design requirement...''
Don't you have this a little backwards? Didn't you mean something like...
``in a system where multiple vendors will be playing with signals, close
adherence to published specifications is all the more important.''?

In fact, the ASDG memory design *IS* forgiving of bus flaws. So forgiving
in fact that it can work in the 86 pin non-Zorro environment. But not so
forgiving as to allow a DMA access to itself to take place at precisely
the WRONG cycle while the board is otherwise so sure that it cannot be
accessed that it is performing a hidden refresh operation.

(Yes, it's true. Slap a scope on the controller and see if you don't see
it emit data at precisely the wrong time. In fact, put your scope probe
on the clock input to the DMA controller and compare it to the clock
driving the bus. Can you spell ``180 degrees out of phase?'' Sure you can.)

>(such as not asserting some signal before cycle X)

Say buddy...that's what makes the whole circus work. What do you think 
a ``cycle'' is? Merely a moment in time provided for the amusement and
possible optional use of the hardware? A ``cycle'' denotes the passage
of time my friend. It signals when a certain activity is and isn't
allowable.

BTW: The same problem is possible to occur between the controller and CHIP
ram with no other boards in the system, though less likely due to the
refresh nature of CHIP ram and its access arbitration. Why doesn't
happen with the Commodore memory board? That design offers completely
hidden refresh (true 0 wait states versus our 0 forced wait states)
and therefore, the memory cycle goes by without that board being ready
for a data access. 

>Personally I've never heard ASDG admit any fault with any of their
>hardware, yet I've never had similar problems with any other memory 
>boards.  

You know, there's a real simple explanation for that. In three years
that our memory design has been out it hasn't gone through a single
mod or revision. Maybe that's because a fault with the design
has yet to be found. 

>Not a flame, just an opinion.  The hardware doesn't work together.  
>Memory boards are easy to find.  I'd stick with the P-p controller.
>I'd replace the memory card.

Be my guest. 

-- 
                        Perry Kivolowitz, ASDG Inc.
ARPA: madnix!perry@cs.wisc.edu   {uunet|ncoast}!marque!
UUCP: {harvard|rutgers|ucbvax}!uwvax!astroatc!nicmad!madnix!perry
CIS:  76004,1765 (what was that about ``giggling teenagers''?)