Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!ucbvax!mtxinu!taniwha!paul
From: paul@taniwha.UUCP (Paul Campbell)
Newsgroups: comp.sys.mac.programmer
Subject: Re: How fast can a MAC-SE drive a serial line?
Keywords: serial, fast
Message-ID: <343@taniwha.UUCP>
Date: 8 Apr 89 00:49:52 GMT
References: <13655@jumbo.dec.com> <28021@apple.Apple.COM> <1514@ccnysci.UUCP> <28564@apple.Apple.COM>
Reply-To: paul@taniwha.UUCP (Paul Campbell)
Organization: Taniwha Systems Design, Oakland
Lines: 50

In article <28564@apple.Apple.COM> phil@Apple.COM (Phil Ronzone) writes:
>In article <1514@ccnysci.UUCP> alexis@ccnysci.UUCP (Alexis Rosen) writes:
>
>Discusssion about LocalTalk and seriol I/O data rates.
>
>>Major nitpick: Both TOPS and Dayna would be surprised to hear that their
>>FlashTalk and DaynaTalk products, which run at 768 to 850 kbps, can't
>>ever go faster than 500 kbps.
>
>The SCC has a clock MAXIMUM of 4 MHz (unless we have changed to a faster
>part lately). The SCC is clocked for baud rate generation at 3.673 MHz.
>AppleTalk, which uses SDLC phsyical transmission, runs as FM0 using the
>onboard PLL -- thus, at around 4MHZ, 230.4 KB is the fastest you can run
>the machine.
>
>In serial I/O, you need to sample at 16X the baud rate. The limiting
>factor is the divisor given to divide the clock rate and still sample at 16X.
>
>The SCC is a pretty interesting USUART, but for the current clock rates,
>SDLC in FM0 can't go faster than 230.4KB -- serial I think (can't remember)
>can be pushed to twice that.

Hi Phil, Alexis ....

	actually there are 2 limits in what the SCC can do, 

	- one is the max speed at which the SCC can be clocked at, either
	  externally (using the clock inputs) or derived from the internal
	  clock (3.672 or whatever). I've driven SCCs at 1MHz output from
	  an internal 4MHz clock. For stnchronous reception you either need
	  an external synchronized clock (direct from the remote transmitter
	  or from an external PLL [ie the external FlashTalk or DaynaTalk
	  boxes]) which is derived from the received signal or from the
	  internal PLL which brings us to the second limit:

	- the internal PLL can't run at much above 230.4 (this magic number
	  comes from the SCC's clock rate which in turn is designed to
	  generate 9600 and all the other baud rates correctly when divided
	  down) because it has to run at 1/16 the SCC's clock rate (which is
	  fixed in the Macs design) in order to do clock recovery


	hence the confusion


	Paul

-- 

Paul Campbell, Taniwha Systems Design, Oakland CA ..!mtxinu!taniwha!paul