Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!ames!pasteur!pine.Berkeley.EDU!hastings
From: hastings@pine.Berkeley.EDU (Mark Hastings)
Newsgroups: comp.sys.next
Subject: NeXT DMA/Memory bandwidth
Keywords: DMA, channels, bandwidth
Message-ID: <12203@pasteur.Berkeley.EDU>
Date: 11 Apr 89 05:09:02 GMT
Sender: news@pasteur.Berkeley.EDU
Reply-To: hastings@pine.Berkeley.EDU (Mark Hastings)
Organization: University of California at Berkeley
Lines: 17


I am hoping that someone can provide a little detailed information about the
specifications of NeXT's "mainframe on a chip."  In particular, I know that
there are 12 DMA channels, which together can take up to 40% of the memory
bandwidth.

What I wanted to find out was:
	1.	What the total memory bandwidth is.
	2.	What percentage of the 40% is allocated to each of the 12
		channels.

I recall seeing a slide at one of the presentations which gave the breakdown,
but I didn't think to copy it down.

Thanks,	
	Mark Hastings
	hastings@ernie.berkeley.edu		..!ucbvax!ernie!hastings