Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!csd4.milw.wisc.edu!lll-winken!uunet!ncrlnk!ncrcae!hubcap!jelynch
From: jelynch@hubcap.clemson.edu (james e lynch)
Newsgroups: sci.electronics
Subject: Reading cycle of 256K dRAM (TMS4256)
Keywords: dynamic memory, bit-line, Single Event Upset
Message-ID: <5044@hubcap.clemson.edu>
Date: 9 Apr 89 05:19:01 GMT
Organization: Clemson University, Clemson, SC
Lines: 10


                                                                                                                                                      
 
                                                                                                                                                                             
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I am working on alpha induced upsets in dynamic random memories.  Currently, I am considering alpha strikes on the bit-lines as a mechanism of depositing chargewhich alters the state of the memory cell.  I am looking of information on the pre-charging of the bit-line before it is connected to the cell.  I am mainly interested in the TMS4256, but will appreciate any information on dRAM architecture and/or timing.  Please reply to my bitnet address

        jelynch@hubcap.clemson.edu