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From: pl@etana.tut.fi (Pertti Lehtinen)
Newsgroups: comp.os.cpm,sci.electronics
Subject: Re: New processor rumour
Message-ID: <6634@etana.tut.fi>
Date: 2 Apr 89 16:32:19 GMT
References: <1055@rpi.edu>
Sender: News@tut.fi
Lines: 36

From article <1055@rpi.edu>, by night@pawl.rpi.edu (Trip Martin):
> 
> Here's a brief rundown of the new architecture from what I remember:
> 
>    * 16 bit bus
>    * 16meg addressibility, although programs still only see the 64k
>      address range of the Z80.  There are 16 page registers for mapping.
>      It can either be done by 8k pages with separate I&D mappings, or
>      4k pages with no distinction between I&D.
>    * Supervisor and user modes
>    * Support for traps and exceptions, including stack overflow, page fault,
>      illegal instruction, etc.
>    * Builtin UART
>    * Hardware programmable wait-states (0-15)
> 

	This one really exists as Z280.
	In addition to those features mentioned above it has:

	* Z80 object code compatible (runs Z80 code)
	* builtin DMA (4-channel)
	* 16-bit or 8-bit bus ( Z-bus or Z80-bus )
	* 10 MHz clock frequency ( future 25 MHz )
	* Support for Coprocessors (FPA-instructions defined)

	Zilog has finally released bugfree version of this.
	(earlier for example DMA and interrupts didn't work)
	( but who needs them, anyway :-)

				Pertti Lehtinen
				pl@tut.fi
	
pl@tut.fi				! -------------------------------- !
Pertti Lehtinen				!  Alone at the edge of the world  !
Tampere University of Technology	! -------------------------------- !
Software Systems Laboratory