Path: utzoo!attcan!utgpu!bnr-vpa!bnr-fos!bnr-public!schow
From: schow@bnr-public.uucp (Stanley Chow)
Newsgroups: comp.arch
Subject: Re: Criteria for comparing RISC processors
Keywords: RISC
Message-ID: <413@bnr-fos.UUCP>
Date: 17 Apr 89 18:52:28 GMT
References: <2368@ogccse.ogc.edu>
Sender: news@bnr-fos.UUCP
Reply-To: schow@bnr-public.UUCP (Stanley Chow)
Organization: Bell-Northern Research, Ottawa, Canada
Lines: 33

In article <2368@ogccse.ogc.edu> johnr@ogccse.ogc.edu (John Roberts) writes:
>I'm interested in evaluation of the current crop of RISC processors based
>on some common criteria.  [...]
>
>Here's the criteria I currently use:
>
>	clock speed
>	transister count
>	on-chip floating point unit? (and/or MFlops of FPU)
>	pipelined execution
>	on-chip caches

My question is: Why this set of criteria?

This looks more like an accessment of the semiconductor technology. You
touch upon the architecture and implementation issues only peripherally.

Would not MIPS, FLOPS, ?h*stones, ... be more useful? If you really have
deep objections to the standard "trivial" benchmarks, devise your own. If
you want to compare raw power, count FLOPS assuming maximal pipeline
occupancy.

BTW, do you consider a high clock speed to be good or bad? [This is a 
serious question. A 100MHz CPU chip will drag in a lot of design issues
that most people would rather not face.]


Stanley Chow        ..!utgpu!bnr-vpa!bnr-fos!schow%bnr-public
		    (613) 763-2831

Oh, that article; I didn't say anything. I was parroting what other
people was saying. How could it be my opinion if I don't even know what
it means?