Path: utzoo!attcan!utgpu!bnr-vpa!bnr-fos!bnr-public!schow
From: schow@bnr-public.uucp (Stanley Chow)
Newsgroups: comp.arch
Subject: Re: Independent Architecture Complilers
Message-ID: <424@bnr-fos.UUCP>
Date: 20 Apr 89 07:26:52 GMT
References: <10441@polyslo.CalPoly.EDU>
Sender: news@bnr-fos.UUCP
Reply-To: schow@bnr-public.UUCP (Stanley Chow)
Distribution: comp
Organization: Bell-Northern Research, Ottawa, Canada
Lines: 28

In article <10441@polyslo.CalPoly.EDU> cquenel@polyslo.CalPoly.EDU (34 more school days) writes:
>
>What if your machine only runs micro-code ?  (This is not an idle
>question).  The term I've heard coined recently is "superscalar".
>If one were to write a compiler for a superscalar machine, it
>seems that one might want to design it a lot like a micro-code
>compiler.
>
>This is NOT an argument for a "retargetable" (ha ha ha ha ha) micro-code
>compiler, just a micro-code compiler.  
>


In my mind, micro-code means that stuff that implements the instructions used
by compilers. Usually, the micro-code also have lots of strange encoding with
parallellism and limited to a small addressing range.

Since I don't know what a superscalar machine looks like, I really can't say
much about it. If your target architecture has "small" instructions that the
compiler must string together to do "big" operations, then you probably want
to get a RISC compiler.


Stanley Chow   ..!utgpu!bnr-vpa!bnr-fos!schow%bnr-public


Opinion? Did I say something in that posting? Wow! Please, can I let that
opinion represent just me? I promise to tell everyone I am the sole representee.