Path: utzoo!dptcdc!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!ucbvax!decwrl!sun!pitstop!sundc!seismo!uunet!portal!cup.portal.com!mslater From: mslater@cup.portal.com (Michael Z Slater) Newsgroups: comp.arch Subject: Re: 486 and 68040 Message-ID: <17315@cup.portal.com> Date: 17 Apr 89 05:05:41 GMT References: <17131@cup.portal.com> <12435@reed.UUCP> Organization: The Portal System (TM) Lines: 30 Mike Rutenberg writes: > I belive the bus structure for the i860 and i486 is the same. > What support chips for the i486 and mc68040 were announced? The i860 bus structure and the i486 bus structure are NOT the same. The 860 bus is 64 bits wide, and the 486 is 32 bits. The 860 provides a "next-near" pin as a hint to page-mode memory controllers, and the 486 does not. The 486 includes bus snooping, and the 860 does not. There may be some similarity in the two buses, but clearly there are many differences. The forthcoming 960CA, on the other hand, may well have a bus similar to the 486's. As for support chips, Intel has announced (but provided no details on) MCA and EISA chip sets for 486-based PCs, and that's about it. Oh, there is a new 32-bit-bus Ethernet chip, the 82596, which is available in a 386 bus flavor and a 486 bus flavor. (The 486 does not offer a pipelined bus mode, and is burst transfer oriented.) Intel has also acknowledged that there will be a cache controller chip for a second-level cache that will work with both the 860 and the 486, but the part is far from being announced. I expect it early next year, as a guess. Motorola has not announced any support chips for the 040. For that matter, they haven't really announced the 040. Moto has never been strong on support chips, though, and I'd be surprised to see much. Michael Slater, Microprocessor Report mslater@cup.portal.com 550 California Avenue, Suite 320, Palo Alto, CA 94036 415/494-2677