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From: prem@crackle.amd.com (Prem Sobel)
Newsgroups: comp.arch
Subject: Re: One aspect of bandwidth (backplane bus)
Message-ID: <25274@amdcad.AMD.COM>
Date: 18 Apr 89 16:50:40 GMT
References: <407@bnr-fos.UUCP> <17500@obiwan.mips.COM> <17527@winchester.mips.COM> <17298@cup.portal.com> <7794@phoenix.Princeton.EDU>
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In article <7794@phoenix.Princeton.EDU> mbkennel@phoenix.Princeton.EDU (Matthew B. Kennel) writes:
>Excuse me, I'm a complete novice in this area, but is it necessary that
>_all_ the memory of each processor be shared, and thus be on a very
>fast and expensive bus?

The real issue is not really cost (at least for some), but speed. No matter
how fast you build the memory, the memory bandwidth will be saturated for
some number of processors. To get unlimited linear speedup one MUST use
local memory and minimize either interprocessor communications or use of
shared memory.

>I guess that in this scheme, there would be some extra physical memory
>riding on the bus for the shared data, but if one really didn't want
>to waste anything, is it possible to have a software-selectable but
>physically implemented device to configure banks of real memory to
>individual processors  or shared pool?

Creve Maples when he was at Lawrence Berekely labs built just suchg a
machine called MIDAS which had reconfigurable memory that could be made
local, shared and dynamically switched. It got quite impressive speedup
and reliability (when the software to support that was done). The real
trick was the reconfigurable interconnects.