Path: utzoo!dptcdc!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!cs.utexas.edu!uunet!cbmvax!daveh From: daveh@cbmvax.UUCP (Dave Haynie) Newsgroups: comp.arch Subject: Re: 486 and 68040 Message-ID: <6628@cbmvax.UUCP> Date: 18 Apr 89 23:13:17 GMT References: <17131@cup.portal.com> Organization: Commodore Technology, West Chester, PA Lines: 144 in article <17131@cup.portal.com>, mslater@cup.portal.com (Michael Z Slater) says: >> query about comments on 68040 and 80486 > Here's my perspective: The 040 and the 486 are very similar in approach. > Both chips use on-chip caches of 8 Kbytes, include snooping for cache > coherency, have on-chip floating-point coprocessors, use pipelining, bypass > gates and other tricks to reduce the average clocks/instruction, and are > supposed to be fully compatible with their predecessors. Both are claimed to > be 2.5 to 3 times as fast as the previous versions (030 or 386) at the same > clock rate. While that's true, I was a bit more surprised about the '486 announcements than that of the '040. It certainly looked, on several major fronts, that the '486 was trying to catch up to the Motorola chips, in terms of system issues (caching, bus sizing, etc) while at the same time coddling the PC clone industry. While the clones are obviously the bread and butter for the '486, it really appears that Intel's designs that work well in an IBM environment also cripple the chip. One can't help but wonder if Intel really wanted the chip crippled anyway. As long as it's faster than a '386, they can help but sell millions, just based on software compatibility. And they stay comfortably distant from any competition with their RISC efforts. Motorola, on the other hand, seems to have taken everything they've learned from RISC and applied that to the design of the '040. If you don't believe it, start at the MMU/Cache differences between the '030 and the '040, and then take a look at the 88100/88200 system. > As to which is faster, there's just not enough public information to call > this one. Intel has not yet released any real performance data. They > have quoted 37,000 Dhrystones and 6.1 MWhetstones at 25 MHz, and 15 to 20 > VAX MIPS. These figures, however, are from simulations. I'll remain > skeptical until we see some measured data. That is the bottom line. Based on what I know, and the fact that I'm seriously Motorola biased, I'd guess that the '040 could seriously outspeed the '486, and it's not just because the '040 can fetch from cache twice as fast (the reason for separate I/D caches, and one of the things I feel was an Intel "sellout to MS-DOS"). > As for the 040, Motorola has not formally introduced the part; they have > made only an "architectural announcement", and have witheld all details. > (They don't even acknowledge the cache sizes officially.) Until the formal > intro this fall, any real evaluation will be impossible. That's true. Though you really can't judge a chip until it's real, no matter what. For example, AMD told us the 29K would do some 42,000 Dhrystones, but there's still no 29K release, last I heard, that had everything in order to actually produce such results. Simulations are a good guideline, but until you have something really running, it's all basically academic. > The differences between the two chips are in several categories: > - The degree to which clocks per instruction has been reduced. Intel's 486 > provides single-clock loads, stores, and moves. Assuming a cache hit, > data can be used by the instruction immediately following the load, with > no stall cycle at all. It remains to be seen if the 040 will do this. Regardless of what Moto's done for new on the '040, if you extend the '030 architecture, you get simultaneous fetch of instruction and data if both caches hit. That's impossible with the single ported cache of the '486. > - Cache architecture. Intel uses an 8K bytes unified cache, which allows them > to support self-modifying code, which is quite common in MS-DOS, Windows, > and OS/2 software. That makes perfect sense, since that's what 95% of the '486 users would be doing with the chip anyway. Though it certainly can have an effect on the chip's performance, which certainly makes Intel's RISC efforts look better (not that they look bad -- I think everyone thinks the 80860 is a neat looking chip, mainly because it doesn't look at all like a traditional Intel chip). Most if not all 680x0 systems outlawed self-modifing code many many moons ago, so the new chips can resort to much more clever caching schemes. > > - Multiprocessor support. Both processors will provide snooping. There are > several issues about second-level cache support, etc., which we > cannot compare until Moto releases full details. The announced '486 "snooping" is pretty primitive. I would have liked it (basically, the ability to invalidate an entry based on a hardware signal) in the '030, but I expect considerably more, something on the order of the 88200 bus snooping (full cache consistency, not just write-through) on the '040. I'll take bets, if anyone's interested.... > Obviously, PC clone vendors will use the 486, and Apple will use the 040. We too. > Vendors of 030-based Unix workstations are likely to use the 040, Especially now that the two top ones, Apollo and HP, are now one. > Sun has said that they will use the 486. (I don't think Sun has said one > way or the other about their plans for the 040.) Same thing they did with the '030 vs. '386 -- they made a big splash about the 386i machine, and quietly introduced the '030 versions of the Sun 3. They were also about the last on the market with '030 machines; maybe a little afraid to compete with their current SPARC, whereas PRISM or the HP Precision Architecture seem significantly distanced from the '030. > Motorola has an edge in the workstation market because there is by far more > workstation software for the 68000 architecture than for any other. However, > ISVs are rapidly porting to RISC architectures and to the 386 architecture. > Furthermore, Intel has a very strong edge in being able to run DOS and OS/2 > software very quickly, in a Unix window if desired. I think that Motorola really has only RISC to worry about, but it's nothing to sluff off, it's a serious threat. Intel's '486 design shows that they're unquestionably targeting the '486 for PCs. > Incidentally, it was striking how much Intel emphasized the 386 at the 486 > announcement. Didn't surprise me a bit. This is the absolute first time that Intel has announced a new 80x86 design that didn't have a completely new architecture piggy-backed on top of an old one. The '486 is really a better '386, whereas the '386 is really a better CISC microprocessor that happens to be able to emulate the '286 and the '086. That's significant; Motorola's been doing virtually the same kind of compatible upgrade thing for years. > The lesson of both of these processors is that CISC can catch up to RISC > performance, it just takes a while. I think RISC will stay a step ahead, > but CISC is not toppin out. And both of these new guys have adopted techniques heretofore only associated with RISC chips. I could be wrong, but I think the culmination of the varied RISC techniques really gives you one thing, when applied right -- a CPU that can be implemented in substantially fewer gates. That's really all that matters. Using the same basic techniques, a 1 micron CMOS 68040 could probably go as fast (or thereabouts) as a 1 micron 88k or MIPS or whatever. But if I come up with some new and better process, there's no question that a 100K design is going to fit in that process long before a 1.2M design. I think that's where RISC is really going to pay off, especially considering how quickly process technology has been moving. > Michael Slater, Microprocessor Report ^^^^ Good Rag! -- Dave Haynie "The 32 Bit Guy" Commodore-Amiga "The Crew That Never Rests" {uunet|pyramid|rutgers}!cbmvax!daveh PLINK: D-DAVE H BIX: hazy Amiga -- It's not just a job, it's an obsession