Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!csd4.milw.wisc.edu!uxc!uxc.cso.uiuc.edu!mcdurb!aglew From: aglew@mcdurb.Urbana.Gould.COM Newsgroups: comp.arch Subject: Re: RT/PC Unaligned Accesses Message-ID: <28200301@mcdurb> Date: 21 Apr 89 17:39:00 GMT Lines: 13 Nf-ID: #R:> >that you can use the low order bits as free tag bits -- without runtime > >> provide a mask that is implicitly ANDed with any {instruction,data} address >> before use -- this way you could place tag bits in the low bits, in the >> high bits, or in any bit you wanted (and not have to rely on features like > >Most instruction addressing modes provide an adder, some also will do >limited shifting. As long as we want AND and OR, let's just put in the >whole ALU. This is sort of what the WM design does with its two opcodes. >Think of one as the addressing mode. You want auto-increment by 17? Pass transistors.