Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!csd4.milw.wisc.edu!lll-winken!lll-lcc!pyramid!epimass!jbuck
From: jbuck@epimass.EPI.COM (Joe Buck)
Newsgroups: comp.arch
Subject: Re: Core Memory
Message-ID: <3105@epimass.EPI.COM>
Date: 21 Apr 89 21:11:40 GMT
References: <1210@twitch.UUCP> <8164@super.ORG> <530@aurora.AthabascaU.CA> <15465@bellcore.bellcore.com>
Reply-To: jbuck@epimass.EPI.COM (Joe Buck)
Distribution: na
Organization: Entropic Processing, Inc., Cupertino, CA
Lines: 12

In article <15465@bellcore.bellcore.com> sjs@ctt.bellcore.com (Stan Switzer) writes:
  >The Honeywell 716 minicomputer (I believe these were once used as ARPA
  >IMPs, but we used one as an RJE station) was designed so that memory
  >would cool fast enough that you could access a core every other cycle
  >without damaging it.  The machine manuals were very explicit in their
  >warnings that getting the machine into a one-instruction loop would
  >fry the instructions core plane (as would an indirect cell pointing to
  >itself).

Ah, the infamous HCF (halt and catch fire) instruction! :-)
-- 
-- Joe Buck	jbuck@epimass.epi.com, uunet!epimass.epi.com!jbuck