Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!ames!lll-winken!uunet!cs.dal.ca!dalcsug!erskine
From: erskine@dalcsug.UUCP (Neil Erskine)
Newsgroups: comp.arch
Subject: Re: Do you have bandwidth?
Keywords: memory bandwidth latency
Message-ID: <396@dalcsug.UUCP>
Date: 21 Apr 89 15:28:32 GMT
References: <407@bnr-fos.UUCP> <7766@thorin.cs.unc.edu> <418@bnr-fos.UUCP> <6658@cbmvax.UUCP>
Reply-To: erskine@dalcsug.UUCP (Neil Erskine)
Organization: Math, Stats & CS, Dalhousie University, Halifax, NS, Canada
Lines: 19

In article <6658@cbmvax.UUCP> jesup@cbmvax.UUCP (Randell Jesup) writes:
>
>	The traditional ways to improve bandwidth are running out of steam,
>or at least starting to.  It's getting harder to keep adding pins to these
>(very large) packages, while still running them at reasonable rates.  Also,
>the signals are getting fast enough that capacitive pad loads from static
>protection (combined with fan-out) are limiting the speed at which you can
>run the lines.
>

	I'm no engineer, but if the capacitive pad loads are
restricting the speed of off-chip signalling, why not dispense with
them, and provide the static protection at the board level?  This
might make board assembly more costly (due to the increased care
required), and the board itself more costly (it might have to be
encased in metal), but if it gives a significant degree of additional
speed, the bother and expense seem worth it.  Alternatively, there may
be some reasons why board level protection can't do the job; in which
case what are those reasons?