Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!ucbvax!agate!crow.Berkeley.EDU!matloff
From: matloff@crow.Berkeley.EDU (Norman Matloff)
Newsgroups: comp.arch
Subject: Re: Do you have bandwidth?
Keywords: memory bandwidth latency
Message-ID: <23649@agate.BERKELEY.EDU>
Date: 26 Apr 89 22:32:15 GMT
References: <407@bnr-fos.UUCP> <7766@thorin.cs.unc.edu>
Sender: usenet@agate.BERKELEY.EDU
Reply-To: matloff@heather.ucdavis.edu (Norm Matloff)
Organization: EECS, UC Davis
Lines: 30

In article <7766@thorin.cs.unc.edu> davis@cs.unc.edu (Mark Davis) writes:
>In article <407@bnr-fos.UUCP> schow@leibniz.uucp (Stanley Chow) writes:

>>In a recent series of articles about address modes and other topics,
>>some posters claim that memory bandwidth is not a problem - to quote
>>Brian Case, "bandwidth can be had in abundance". I happen to think that
>>we do not enough bandwidth now. What to other people think?

>You can always improve bandwidth with silicon (and wires).  To double
>bandwidth, double the data bus size.  You can also use interleave or
>special chip modes (static column or page mode access) to improve
>bandwidth.

These measures, e.g. wider buses, may just shift the bottleneck to 
something else.  There is still a strong limitation on a chip's 
number of pins, right?  The area of a rectangle grows much faster 
than the perimeter, and of course there are mechanical reasons why 
pins can't be too small.  Thus the ratio of number of I/O channels
of a chip to bits stored in the chip will probably get worse, not
better.

We are developing an optical interconnect which has plenty of bandwidth,
since it bypasses the pins and reads from the chip directly [see 1988
ACM Supercomputing Conf.]  But it does indeed seem to us  --  at this
stage, at least  --  that huge bandwidth can not be exploited fully in
many, maybe most, applications.

I certainly would like to hear what others have to say about this.

   Norm