Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!ames!lll-winken!uunet!tektronix!orca!tekecs!frip!andrew
From: andrew@frip.wv.tek.com (Andrew Klossner)
Newsgroups: comp.arch
Subject: Re: Sustained Performance Computer Architecture
Message-ID: <11342@tekecs.GWD.TEK.COM>
Date: 26 Apr 89 18:22:56 GMT
References: <14292@duke.cs.duke.edu>
Sender: andrew@tekecs.GWD.TEK.COM
Organization: Tektronix, Wilsonville, Oregon
Lines: 25

[]

	"A new general-purpose computer architecture with sustained
	instruction pipeline performance (regardless of program flow
	changes) has been developed at the Digital Systems Laboratory
	of the Department of Electrical Engineering at Duke University
	... The execution unit (EU) of the new architecture can be that
	of any typical von Neumann computer. The instruction fetch and
	decode operations are performed by multiple instruction decode
	units (IDU) which prefetch all potentially needed instructions
	... The decoded segments are ready for execution at all times,
	hence there are no bubbles in the instruction pipeline, and no
	I-cache misses."

Never an instruction miss?  What happens when executing code for a
switch statement, such as:

	load	r2,jumptable(r1)
	jmp	r2

The number of IDUs required to avoid all instruction misses would seem
to be unbounded.

  -=- Andrew Klossner   (uunet!tektronix!orca!frip!andrew)      [UUCP]
                        (andrew%frip.wv.tek.com@relay.cs.net)   [ARPA]