Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!ucbvax!amdcad!rpw3 From: rpw3@amdcad.AMD.COM (Rob Warnock) Newsgroups: comp.arch Subject: Re: Metastability Message-ID: <25423@amdcad.AMD.COM> Date: 27 Apr 89 09:27:54 GMT References: Reply-To: rpw3@amdcad.UUCP (Rob Warnock) Organization: [Consultant] San Mateo, CA Lines: 46 josh@klaatu.rutgers.edu (J Storrs Hall) writes: +--------------- | One commonly reads in articles about arbiter circuits that | it has been proven that the problem of metastability cannot | be completely avoided. Is there an actual proof anywhere? | --JoSH +--------------- The way I heard it, just as momentum & position are "conjugate" quantities subject to Heisenberg Uncertainty limits if you try to measure both at the same time, so are energy & time. A synchronizer tries to measure with absolute precision whether an energy (the "AND" of data and clock, typically) is above or below a threshold, and tries to do the measurement in a finite time. You can't do both. So that's the impossibility, at some very fundamental level. But most real synchronizers have failure rates far worse than the Heisenberg limit... Most of the circuits I've seen that claimed to "solve" the sychronizer problem either (1) simply pushed the energy-threshold decision around to a part of the circuit where you normally wouldn't think to look for it ("solution" by sweeping under the rug -- but the dirt's still there), or (2) "hide" the fact that they can delay making a decision for a while in some cases. The real trick to making a good (not perfect) synchronizer is getting a latch stage with a very high gain-bandwidth product "around the loop". This shows up as a small "rho" parameter in the MTBF equation. There are published papers (especially the one by Tom Cheney, at U Wash.) which give measured parameters of "delta" (a.k.a. "t0") and "rho" for various commercial parts. (The Fairchild 74F74 & 74F374 and AMD Am298xx parts are pretty good. I generally don't use anything else.) You can also make a two-stage synchronizer, where the second stage can fail only if the first stage comes out of metastable just as the second stage clocks. [You have to bias the output of the first stage so a first- stage metastable looks like a clean one or zero to the second stage.] Depending on your environment, this is sometimes better than clocking a single-stage synchronizer at 1/2 the rate. Rob Warnock Systems Architecture Consultant UUCP: {amdcad,fortune,sun}!redwood!rpw3 DDD: (415)572-2607 USPS: 627 26th Ave, San Mateo, CA 94403