Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!iuvax!rutgers!cbmvax!daveh
From: daveh@cbmvax.UUCP (Dave Haynie)
Newsgroups: comp.sys.amiga.tech
Subject: Re: Need advice on hardware projects
Message-ID: <6678@cbmvax.UUCP>
Date: 24 Apr 89 17:19:46 GMT
References: <7922@killer.Dallas.TX.US>
Organization: Commodore Technology, West Chester, PA
Lines: 52

in article <7922@killer.Dallas.TX.US>, elg@killer.Dallas.TX.US (Eric Green) says:

> Maybe someone on the net could help by digging up chip #s/manufactures
> for refresh controllers. I just wish to point out that doing a memory
> board that connects to a 25mhz 68020/68030 is very different from
> doing a memory board that slaps on the side of an Amiga 1000....

Absolutely true.  While you have more concerns about noise at those speeds,
the main problem is the handling of refresh.  With a simple, normal speed
SOTS memory card for the A1000, it's possible to interleave memory access
with refresh, much as the CHIP memory works, and still run full speed with
cheap (150ns) memories.  Once you even get to 14.3MHz on a 68020, even 100ns
parts aren't fast enough on their own to give you no wait state operation,
and they way you handle refresh can slow this down even more.  Refresh is
basically another arbitration problem -- the 68020 wants the memory bus most
of the time, but you need to supply a refresh to keep things going or you're
in big trouble.  Thing is, you never know when the 68020 will be using the
memory, and you probably don't know just when a refresh cycle is going to
come along.  Most of the design cleverness, on this level, is how you create
an artifical time at which both the status of the 68020 cycle (either 
definitely in or definitely out of a cycle) and refresh are known long 
enough to prevent the other from taking place.  There are lots of ways to
solve this problem.  A controller chip will do this for you, but they can
be expensive and possibly either slow or uncooperative.

The other half of a fast memory system is in making it as fast as you can
using the slowest memory parts you can get away with that are also the 
fastest memory chips you can afford.  There's on-chip support of special
addressing modes in most DRAM -- the fast page, nybble, or static column
modes you sometimes hear about.  There are also architectural decisions on
memory structure that may influence speed.  And it's often a tradeoff 
between the number of chips, the complexity of the support logic, and the
speed of the memory board; eg, adding more chips and/or more, clever 
support logic can result in a faster board.  If you need a 4 meg board you
can use nybble DRAM with a 68030 and get extra speed for very little extra
logic.  If you need a 1 meg board, you could get the same or possibly a
better speedup using static column memories, but the support logic is much
more complex.  

Juding 32 bit memory speed is going to be interesting.  For example, most of
the design enhancements have some form of locality of reference which could
result, for instance, in board A being faster than board B for linear access,
but board B coming out on top if you access every 2nd or 4th memory
location.

> |    // Eric Lee Green              P.O. Box 92191, Lafayette, LA 70509     |
> |   //  ..!{ames,decwrl,mit-eddie,osu-cis}!killer!elg     (318)989-9849     |
> | \X/            Amiga.  The homestation for the blessed of us.             |
-- 
Dave Haynie  "The 32 Bit Guy"     Commodore-Amiga  "The Crew That Never Rests"
   {uunet|pyramid|rutgers}!cbmvax!daveh      PLINK: D-DAVE H     BIX: hazy
              Amiga -- It's not just a job, it's an obsession