Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!ucbvax!decwrl!labrea!polya!rokicki
From: rokicki@polya.Stanford.EDU (Tomas G. Rokicki)
Newsgroups: comp.sys.amiga.tech
Subject: Re: blitter operation speeds
Keywords: blit,need,for,speed,spam
Message-ID: <8768@polya.Stanford.EDU>
Date: 25 Apr 89 23:42:10 GMT
References: <4087@ucdavis.ucdavis.edu>
Sender: Tomas G. Rokicki <rokicki@polya.Stanford.EDU>
Reply-To: rokicki@polya.Stanford.EDU (Tomas G. Rokicki)
Distribution: comp.sys.amiga.tech
Organization: Stanford University
Lines: 44

> Hi there,

Howdy, howdy!

> Mainly, what is the difference in speed between doing a full A+B+C->D
> blit and a simple A->D operation? Does the blit go faster if the
> dma is turned off (reusing the same data) for one or two channels
> in a A+B+C->D operation?

Yep.  Simply stated:

   minimum cycle is 4 clocks (7.16MHz clocks)
   use of A always costs 2
   use of B is always free
   use of C or D is free
   use of C and D costs 2

So, we end up with the following table:

        Channel   Clocks/
        enabled   blitter
        A B C D   cycle
        -------   -------
        N N N N     4
        N N N Y     4
        N N Y N     4
        N N Y Y     6
        N Y N N     6
        N Y N Y     6
        N Y Y N     6
        N Y Y Y     8
        Y N N N     6
        Y N N Y     6
        Y N Y N     6
        Y N Y Y     8
        Y Y N N     6
        Y Y N Y     6
        Y Y Y N     6
        Y Y Y Y     8

Note that you still contend for DMA cycles, so these are maximum speeds.
Line mode always runs in 8-clock cycles.

-tom