Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!ucbvax!decwrl!labrea!polya!rokicki
From: rokicki@polya.Stanford.EDU (Tomas G. Rokicki)
Newsgroups: comp.sys.amiga.tech
Subject: Re: blitter operation speeds
Keywords: blit,need,for,speed,spam
Message-ID: <8770@polya.Stanford.EDU>
Date: 25 Apr 89 23:49:34 GMT
References: <4087@ucdavis.ucdavis.edu> <8768@polya.Stanford.EDU> <8769@polya.Stanford.EDU>
Sender: Tomas G. Rokicki <rokicki@polya.Stanford.EDU>
Distribution: comp.sys.amiga.tech
Organization: Stanford University
Lines: 14

> My mistake; the fifth through eighth lines should read:

It gets worse.  Completely ignore my previous articles.  Here's the
scoop:

Minimum blitter cycle is four clocks (7.18MHz clocks.)
*A* is always free.
*B* always costs 2 cycles.
C or D is always free.
C and D costs two cycles.

Gotta get this right!

-tom