Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!ucbvax!decwrl!labrea!polya!kaufman
From: kaufman@polya.Stanford.EDU (Marc T. Kaufman)
Newsgroups: comp.sys.mac.programmer
Subject: Re: How fast can a MAC-SE drive a serial line?
Keywords: serial, fast
Message-ID: <8470@polya.Stanford.EDU>
Date: 15 Apr 89 01:29:28 GMT
References: <13655@jumbo.dec.com> <28021@apple.Apple.COM> <1514@ccnysci.UUCP> <28564@apple.Apple.COM> <1581@ccnysci.UUCP>
Sender: Marc T. Kaufman <kaufman@polya.Stanford.EDU>
Reply-To: kaufman@polya.Stanford.EDU (Marc T. Kaufman)
Organization: Stanford University
Lines: 37

In article <1581@ccnysci.UUCP> alexis@ccnysci.UUCP (Alexis Rosen) writes:

->The SCC has a clock MAXIMUM of 4 MHz (unless we have changed to a faster
->part lately). The SCC is clocked for baud rate generation at 3.673 MHz.
                                                      make that 3.6864 MHz
->AppleTalk, which uses SDLC phsyical transmission, runs as FM0 using the
                        SDLC Framing...
->onboard PLL -- thus, at around 4MHZ, 230.4 KB is the fastest you can run
->the machine.

->In serial I/O, you need to sample at 16X the baud rate. The limiting
    ^asynchronous
->factor is the divisor given to divide the clock rate and still sample at 16X.

->The SCC is a pretty interesting USUART, but for the current clock rates,
->SDLC in FM0 can't go faster than 230.4KB -- serial I think (can't remember)
->can be pushed to twice that.

Synchronous data can run at clock/4, or 921.6 Kbps, with an External clock.
The limiting factor is the internal state machine in the SCC, which needs at
least 4 clocks per bit to move things about.

>Hm. Something I don't know about. What is "FM0" in this context?

FM (biphase) coding is a coding scheme wherein there is a change of state
(mark to space or space to mark) at the boundaries (beginning and end of each
bit timing cell), and, for FM0, a change of phase in the middle of the cell
for '0' bits.  For FM1, '1' bits get a change in the middle. If you think of
FM as Frequency Modulation, you will see that a stream of '1's is a square
wave at 115.2 KHz, and a stream of '0's is a square wave at 230.4 KHz.  Digital
phase lock loops work very reliably on such stuff.  There is such a DPLL in
the SCC.

BTW: the SCC can also lock on "REAL" SDLC (the NRZI kind) but the frequency
spectrum is not as tight, so it's harder to put through transformers.

Marc Kaufman (kaufman@polya.stanford.edu)