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From: bayes@hpfcdc.HP.COM (Scott Bayes)
Newsgroups: comp.sys.mac.programmer
Subject: Re: Re: XFCN/XCMD string in LSC C v3.0
Message-ID: <11550008@hpfcdc.HP.COM>
Date: 14 Apr 89 23:43:36 GMT
References: <28737@ucbvax.BERKELEY.EDU>
Organization: HP Ft. Collins, Co.
Lines: 9

As far as I know the cache-line is 4 longwords in the 68030 d and i-caches.
This is 128 bits, and is aligned to quad-longword boundaries. If there's a
cache miss, the address you wanted is loaded first, then the remaining
data in the cache line is loaded into the cache while the CPU messes with the
data just loaded. Of course, all flushes also happen on quad-longword
boundaries as well. You really want a 32-bit wide data bus in the machine
to take advantage of this.

Scott Bayes