Path: utzoo!dptcdc!jarvis.csri.toronto.edu!mailrus!ames!lll-lcc!pyramid!cbmvax!daveh
From: daveh@cbmvax.UUCP (Dave Haynie)
Newsgroups: sci.electronics
Subject: Re: FSF/AT-bus architecture
Message-ID: <6604@cbmvax.UUCP>
Date: 17 Apr 89 18:46:44 GMT
References: <1758@wpi.wpi.edu>
Organization: Commodore Technology, West Chester, PA
Lines: 29

in article <1758@wpi.wpi.edu>, jhallen@wpi.wpi.edu (Joseph H Allen) says:
> And now for my 2 cents' worth:  If I had designed the IBM PC bus.... ( :-) it
> would be something like this:

	[goes on to describe desired PC bus signals]

Things also missing:

SLAVE*		Asserted by a card when it's responding to an address.  Each
		slot has it's own.  This means that bus control hardware is
		capable of detecting when two cards try to respond to the
		same address.  It also lets you do other neat things...

Take the stuff you mentioned, the SLAVE signal above, change DMA a little,
and you're pretty close to the Amiga expansion bus.  Amiga cards also have
a mechanism that lets software poll them and figure out how much space they
need, then locate them in space required, providing there is enough space
left in the area reserved for expansion.

> Issues to resolve:  how to expand the data bus
> 		    how to interrupt other than the default processor

If you're starting to think about multiple CPU systems on the bus, you
need to consider how to support cache consistency.  

-- 
Dave Haynie  "The 32 Bit Guy"     Commodore-Amiga  "The Crew That Never Rests"
   {uunet|pyramid|rutgers}!cbmvax!daveh      PLINK: D-DAVE H     BIX: hazy
              Amiga -- It's not just a job, it's an obsession