Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!ames!ncar!boulder!unicads!les
From: les@unicads.UUCP (Les Milash)
Newsgroups: comp.arch
Subject: Re: RISC and emulated languages
Message-ID: <408@unicads.UUCP>
Date: 28 Apr 89 16:50:52 GMT
References: <158@bms-at.UUCP> <4015@ficc.uu.net>
Reply-To: les@unicads.UUCP (Les Milash)
Organization: Unicad  Boulder, CO
Lines: 16

In article <4015@ficc.uu.net> peter@ficc.uu.net (Peter da Silva) writes:
>In article <158@bms-at.UUCP>, stuart@bms-at.UUCP (Stuart Gathman) writes:
>> [...] emulation/interpretion on RISCs [...]
the scheme-("screme")-on-88K article in ASPLOS-III is neat
>
>
>Wow, the 1802 looks RISCier all the time.
----------^^^^ chough choke ghasp!  yes it fully exposes 
starvation-for-data to the compiler.  this is the chip
for which the term "memory bottlewidth" was coined.  
i'm kind of fond of it, tho; single-step in hardware,
would run off a lantern battery, would run at .1Hz
(for hands-off single-stepping) if you had one of them
RC clocks.

moLester