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From: roger@wraxall.inmos.co.uk (Roger Shepherd)
Newsgroups: comp.arch
Subject: Re: critical path of FP chips
Message-ID: <1343@brwa.inmos.co.uk>
Date: 28 Apr 89 08:59:12 GMT
References: <100524@sun.Eng.Sun.COM> <18106@obiwan.mips.COM>
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Reply-To: roger@inmos.co.uk (Roger Shepherd)
Organization: INMOS Limited, Bristol, UK.
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In article <18106@obiwan.mips.COM> mark@mips.COM (Mark G. Johnson) writes:
>In article <100524@sun.Eng.Sun.COM>, dgh%dgh@Sun.COM (David Hough) writes:
>   > I have heard that adder carry propagate time and multiplier array
>   > size are the key constraints with a floating-point chip; ....
>Well, only true for those chips which don't have an explicit hardware
>divide unit, e.g. Clipper, Intel 860, TI 8847, Moto 88K, Transputer.
                                                          ^^^^^^^^^^^
>These folks use the multiply and the add hardware, plus a Newton-Rhapson
>iterative algorithm, to synthesize division.  

Can I correct this. The T800 transputer does not have a multiplier or
divider as such. Both operations are performed iteratively, the multiplication
generating 3 bits of product per cycle, the divider generating 2 bits of
quotient per cycle. I should point out that the T800 FPU was designed to fit 
into a very small area (about 20 sq mm); the T800 was announced in 1987 and
it contains an integer processor, 4 communication links and 4k bytes of
on-chip RAM. At the time the die (about 1 sq cm) was the largest we could 
contemplate manufacturing - it was die size as much as anything which 
determined the implementation; large array multipliers were out.


Roger Shepherd, INMOS Ltd   JANET:      roger@uk.co.inmos 
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