Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!cs.utexas.edu!uunet!mcvax!dik
From: dik@cwi.nl (Dik T. Winter)
Newsgroups: comp.arch
Subject: Re: CDC 205 et al
Message-ID: <8069@boring.cwi.nl>
Date: 30 Apr 89 17:04:40 GMT
References: <568309@vaxa.uwa.oz>
Organization: CWI, Amsterdam
Lines: 24

In article <568309@vaxa.uwa.oz> g_ahrendt@vaxa.uwa.oz writes:
 > 1. In regard to an article posted a while back stating that the CDC CYBER 205 is
 > slower than a Cray 1. This is incorrect. The CDC CYBER 205-424 has been clocked 
 > around 800 MIPS, making it faster than the Cray 1, ETA10-P, ETA10-Q, NEC SX-1, 
 > Cray X/MP-2, IBM Sierra 3090-400/VF, NEC SX-1E.....
 > 
I think that this posting uses another definition of MIP.  To wit:  to
execute at 800 MIPS you need either a 1.2 nsec cycle (or better) or multiple
instructions per cycle.  The Cyber 205 has neither.  So it would be best if
the poster posted his definition of MIPS.  And then the remainder can question:
`why another definition of MIPS?'; oh well, as long as it remains meaningless.
Unless the poster intended MFLOPS instead.

 > This is also incorrect, whereas the following gives a more accurate picture, 
 > based on machines actually available, and not scheduled for production.
 > 
 > 1. ETA               US 10-G       10.3 Billion Instructions per Second 
This machine is certainly not scheduled for production.  But I did not
know it was intended to have a 97 psec cycle.  Or are you going
multiprocessor?  This would mean a 32 processor ETA; strange.
-- 
dik t. winter, cwi, amsterdam, nederland
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