Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!ncar!ames!oliveb!sun!fatcity!khb
From: khb@fatcity.Sun.COM (Keith Bierman Sun Tactical Engineering)
Newsgroups: comp.arch
Subject: Re: Bandwidth and RISC vs. CISC
Message-ID: <102025@sun.Eng.Sun.COM>
Date: 1 May 89 02:41:25 GMT
References: <38853@bbn.COM> <423@bnr-fos.UUCP>
Sender: news@sun.Eng.Sun.COM
Reply-To: khb@sun.UUCP (Keith Bierman Sun Tactical Engineering)
Organization: Sun Microsystems, Mountain View
Lines: 40

In article <423@bnr-fos.UUCP> schow@bnr-public.UUCP (Stanley Chow) writes:
> ... cogent argument deleted..
>
>I can hear it now, everyone is jumping up and down saying, "what a fool,
>doesn't he know that all those cycles are free?", "Hasn't he heard of 
>pipelining and register scoreboarding?", "but the CISC instruction are slower
>so the RISC will still run faster." 
> ... and more

>"Compilers can do optimizations", I hear the yelling. This is another
>interesting phenomenon - reduce the complexity in the CPU so that the 
>compiler must do all these other optimizations. I have also now seem any
>indications that a compiler can to anywhere close to an optimal job on
>scheduling code or pipelining. Even discounting the NP-completeness of
>just about everything, theoratical indications point the other way,
>especially when the compiler has to juggle so many conflicting constraints.
>

Cydrome and Multiflow have both demonstrated that it is possible to
move much of the analysis to the compiler (with a increase in compile
times :>). 

The original paper on the Bulldog compiler by ellis (well, its a book
:>) describes how the memory bandwidth problem can be dealt with, and
in many cases quite well.

The Cydra 5 compiler could, in interesting programs (but by no means
all) generate optimal code for key loops (as long as the vector were
long; but this was a hardware constraint, not a compiler issue).

It should be noted that both Cydrome and Multiflow chose to have an
almost fully exposed pipeline, and no scoreboarding or other nastiness.

Memory bandwidth is key to deleivering high performance, but the
RISCiness or CISCiness of the processor (only impacting the
instruction side of things) would seem to be a non-issue.
Keith H. Bierman      |*My thoughts are my own. Only my work belongs to Sun*
It's Not My Fault     |	Marketing Technical Specialist 
I Voted for Bill &    |   Languages and Performance Tools. 
Opus            (* strange as it may seem, I do more engineering now     *)