Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!ucbvax!pasteur!ames!netsys!vector!chip
From: chip@vector.Dallas.TX.US (Chip Rosenthal)
Newsgroups: comp.arch
Subject: Re: Connecting chips
Keywords: wafer interconnect stacking bonding
Message-ID: <108@vector.Dallas.TX.US>
Date: 1 May 89 03:25:30 GMT
References: <407@bnr-fos.UUCP> <7766@thorin.cs.unc.edu> <23649@agate.BERKELEY.EDU> <4852@pt.cs.cmu.edu>
Reply-To: chip@vector.Dallas.TX.US (Chip Rosenthal)
Organization: Dallas Semiconductor
Lines: 17

<4852@pt.cs.cmu.edu> lindsay@MATHOM.GANDALF.CS.CMU.EDU (Donald Lindsay) writes:
>matloff@heather.ucdavis.edu >	(Norm Matloff) writes:
>>There is still a strong limitation on a chip's number of pins, right?
>I think that solutions are coming along nicely.

There are some techniques available in manufacturing now for very dense
systems.  The most common is "chip-on-board".  There are two big problems
with these techniques.  The first is reliability, mainly hermiticity.  A
lot of work has been put into garden-variety run-of-the-mill plastic DIP
packages to get them to an acceptable point.  It's going to be a bit
before some of these advanced techniques can stand up to the same
environmental stresses.  The second problem is testability.  It all goes
back to the controlability/observability issue.  As you start stacking
more and more circuitry between you and the circut under test, this becomes
a nontrivial problem.
-- 
Chip Rosenthal / chip@vector.Dallas.TX.US / Dallas Semiconductor / 214-450-5337