Path: utzoo!mnetor!tmsoft!dptcdc!berner!lethe!dave
From: dave@lethe.UUCP (Dave Collier-Brown)
Newsgroups: comp.arch
Subject: Re: One aspect of bandwidth (backpl
Message-ID: <2388@lethe.UUCP>
Date: 29 Apr 89 22:35:25 GMT
References: <2222@lethe.UUCP> <28200304@mcdurb>
Reply-To: dave@lethe.UUCP (Dave Collier-Brown)
Organization: Interleaf Canada, News courtesy of Systems Software
Lines: 29


>>  Well, sort of.
>>  You do charge several millions, but you don't so much build a bus as
>>you do a star, with the memory in the middle and the processors out on
>>the arms.  The thing in the middle is called a system controller on a 'bun
>>and costs a non-trivial amount of money.

In article <28200304@mcdurb> aglew@mcdurb.Urbana.Gould.COM writes:
>Now that there is no bus to snoop on, cache coherence between caches at the 
>ends of the arms of the star [?] becomes problematic.  Start looking at
>software managed cache coherency, or strictly private memory. 
[several more reasonable alternatives left out]

  If memory serves, there is no true cache on the DPS-8 processor, but there
is some sort of load/store consistancy logic. There is supposed to be a quite
normal-looking cache **in the controller** of the NEC-designed DPS 90s, but I
know so little about the new machines that this may be completely wrong.  I
don't work on honeybuns any more (alas!).
  Does anyone know the cache consistancy scheme on the DPS-90 or the
NEC/Honeywell supercomputer?

--dave


-- 
David Collier-Brown,  | {toronto area...}lethe!dave
72 Abitibi Ave.,      |  Joyce C-B:
Willowdale, Ontario,  |     He's so smart he's dumb.
CANADA. 223-8968      |